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DMA controller (DMA)
RM0008
10.3.7
DMA request mapping
DMA1 controller
The 7 requests from the peripherals (TIMx[1,2,3,4], ADC1, SPI1, SPI/I2S2, I2Cx[1,2] and
USARTx[1,2,3]) are simply logically ORed before entering DMA1, this means that only one
request must be enabled at a time. Refer to Figure 23: DMA1 request mapping .
The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.
Figure 23. DMA1 request mapping
Peripheral
Fixed hardware priority
request signals
High priority
ADC1
TIM2_CH3
TIM4_CH1
USART3_TX
TIM1_CH1
TIM2_UP
HW request 1
SW trigger (MEM2MEM bit)
Channel 1 EN bit
HW request 2
Channel 1
Channel 2
TIM3_CH3
SPI1_RX
USART3_RX
SW trigger (MEM2MEM bit)
Channel 2 EN bit
TIM1_CH2
TIM3_CH4
TIM3_UP
SPI1_TX
USART1_TX
TIM1_CH4
HW request 3
SW trigger (MEM2MEM bit)
Channel 3 EN bit
Channel 3
internal
DMA1
TIM1_TRIG
TIM1_COM
TIM4_CH2
SPI/I2S2_RX
HW request 4
SW trigger (MEM2MEM bit)
Channel 4
request
I2C2_TX
Channel 4 EN bit
USART1_RX
TIM1_UP
SPI/I2S2_TX
TIM2_CH1
TIM4_CH3
HW request 5
SW trigger (MEM2MEM bit)
Channel 5
I2C2_RX
Channel 5 EN bit
USART2_RX
TIM1_CH3
TIM3_CH1
TIM3_TRIG
HW REQUEST 6
SW TRIGGER (MEM2MEM bit)
Channel 6
I2C1_TX
Channel 6 EN bit
USART2_TX
TIM2_CH2
TIM2_CH4
TIM4_UP
HW request 7
SW trigger (MEM2MEM bit)
Channel 7
Low priority
I2C1_RX
Channel 7 EN bit
Table 57 lists the DMA requests for each channel.
188/995
Doc ID 13902 Rev 9
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